1. Field of the Invention
The present invention relates to a memory circuit and, more particularly, to a circuit for accessing a display memory employed in a display apparatus such as a CRT or an LED.
2. Description of the Related Art
A memory circuit for a display apparatus is provided with a RAM as a display memory which stores display data having a one-to-one correspondence with respect to each dot or pixel on a display screen. Display data are thus written into the RAM by a CPU.
Upon turning a power supply on or in order to clear the display screen, it is often required to write blank data into all the bits of the RAM as a clear operation. To this end, all the addresses of the RAM are required to be sequentially selected one by one for access.
Referring to FIG. 4, a memory circuit according to a prior art includes a four-bit counter 1 for generating a display clock CD and a set of select signals SS in response to a clock CK, an address counter 2 for generating a set of address signals A0 to An for accessing a RAM 3 storing display data, a parallel-to-serial converter 4 for converting data supplied thereto into serial data DS in response to the select signals SS; and a data switching circuit 5 selecting one of display data DD and blank data DB and supplying the selected data to the display RAM 3 in response to a clear signal SC.
In operation, the counter 1 frequency-divides the clock CK at a rate of 1/16 and generates a clock signal CA which is in turn supplied to the address counter 2. The address counter 2 thus generates address signals A0 to An in response to the clock CA and sequentially reads the data in the RAM 3 by using the address signals A in synchronism with the display scan period. The parallel-to-serial converter 4 converts the thus-read parallel data DR into the serial data DS in response to the select signal SS composed of most significant three bits of the frequency-divided output of the clock CK from the counter 1.
In the normal display mode, the data switching circuit 5 selects the display data DD as the write parallel data DW for the RAM 3. Upon being supplied the clear signal SC, the data switching circuit 5 switches to select the blank data DB as the write parallel data DW in response to the supply of the clear signal SC and clears the RAM 3 by following the address signal A and writing the blank data DB in the RAM 3 in synchronism with the display scan period. In order to rewrite all the data in the RAM 3 with the blank data DB, a time for one frame corresponding with the display time for one screen, i.e., approximately 10 mS is thus required.
In this manner, the time required for clear operation depends on the display time for the display screen in the first conventional memory apparatus.
On the other hand, in this type of information processing apparatus, the request for the high speed processing is enhanced, and the clear operation of the display RAM in this display apparatus is not an exception.
Referring to FIG. 5 which is the block diagram showing a second memory apparatus disclosed in Japanese Patent Laid-open Publication No. Hei 4-259990 intending to increase the speed of the clear operation, this second conventional memory apparatus is provided with: an address generating portion 102 for sequentially addressing all the memory cells in a RAM 101 for each external clock by clear signals; and a controlling portion 103 for controlling the input and output of the same value with respect to an assigned address, and automatically clears and checks the RAM 101 by only the input of clear signals CLR. As described above, the second memory apparatus additionally includes the address generating portion and the controlling portion exclusively for the clear operation as well as the regular elements.
Similarly, referring to FIG. 6 which is a block diagram showing a third conventional memory apparatus disclosed in Japanese Patent Laid-open Publication No. Hei 2-089291 intending to increase the speed of the clear operation, the third conventional memory apparatus is a SRAM having an address decoder for selecting an arbitrary memory cell from the memory cells and provided with a clear function circuit which suppresses the address decoder in response to the clear signal and activates all the memory cells to write the same data. The clear operation of the SRAM is not based on the external data setting but completely processed within the RAM so that the cell base of the direct memory is operated to clear the data. Accordingly, since it is necessary to add the clear function to the internal circuit of the RAM itself, this apparatus is not of the general type.
Since the above-describe first conventional memory apparatus writes the blank data by sequentially selecting all the addresses of the display RAM one by one in synchronism with the display scan period in order to perform the clear operation, the time required for the clear operation depends on the display time of the display screen, thus taking much time.
Further, in the second conventional memory apparatus intending to increase the speed of the clear operation, the need for the address generating portion and the controlling portion exclusively for the clear operation which are unnecessary at the time of regular data writing/reading operation leads to the large circuit dimension.
Furthermore, in the third conventional memory apparatus intending to increase the speed of the clear operation, since the clear function which clears the data by operating the cell base of the direct memory must be additionally provided within the internal circuit of the display RAM, this apparatus is not general.